1. Field of the Invention
The present invention relates generally to integrated circuits and methods of integrated circuit construction that provide attenuation of current surges, and more specifically to improved systems and method of chip design and package implementation for attenuating the effects of ground current surges in timing circuits.
2. Description of Related Art
In general, timing circuits are susceptible to surrounding circuit noise, which oftentimes increase the “jitter” of the oscillation frequency and phase of the desired timing signal. With the placement of increasing quantities of timing circuits and/or system clocks, for example phase-locked loops (PLLs) and delay-locked loops (DLLs), within the confines of each chip, the necessity of considering noise reduction for each timing circuit becomes increasingly important.
Specifically, capacitive filters alone between supply and ground have been shown not to relieve the root causes of power supply and ground noise. Further, capacitive coupling by way of Electro-Static Discharge (ESD) structures to sensitive timing circuits is a liability.
Additionally, system clocks are sensitive to all power supply and ground noise as well as noise from certain types of drivers, whether that noise is generated externally or internally to the integrated circuit chip. Thus, the supply and grounding methods for system clocks on an integrated circuit (“IC”) chip, such as the PLLs and DLLs, are frequently isolated from the board supply and ground with inductive filters. Individual circuits of the PLL and DLL, such as voltage-controlled oscillators (VCOs), phase detectors, dividers, and charge pumps, then, are isolated from each other when integrating these circuits onto a single silicon chip.
Building upon the short-sighted foundational precepts of the subject isolation and grounding technologies, the direction promulgated by suppliers understandably also fails to present credible solution to the current noise problems. Specific instructions from vendors offering timing circuits, such as PLL (phase-lock loops) and DLL (delay-lock-loops) separate power supply nodes, ground nodes for the componenets of these circuits, i.e., the phase detector, voltage controlled oscillator, divider, and driver circuits. These circuits in turn isolate the supply and ground nodes of the chip core circuits from the timing circuits.
The teaching of this invention is consistent with vendor instructions only in so far as requiring separate power supplies but differ in that individual ground nodes are electrically tied to a common node.
In recent years, the combination of factors such as substrate noise induced by high current output drivers on the chip and power supplies with low voltage supply potentials has been shown to cause timing circuits to malfunction.
The magnitude of a timing circuit malfunction can be measured by the distortion of the circuit's clock periods and is often expressed in terms of “jitter”. “Jitter” is the difference in phase between adjacent clock cycles in a cycle-to-cycle measurement, or between clock cycles separated by a specific number of intervening cycles. The latter measurement is termed “long-term cycle drift”. In essence, then, a timing circuit's sensitivity to noise can be expressed in terms of clock jitter.
Clock jitter, given by the compression and expansion in a series of adjacent clock periods, can limit the time allotted for logic delays bounded between rising and falling clock edges. Jitter affects the overall operation of any given clock circuit, inter alia, by limiting the maximum operating frequency of the chip.
With respect to the isolation of clock jitter, power supplies in the range of 1.0 to 1.2 volts limit the headroom, and do not allow the use of current source isolation. In higher voltage supplies, e.g., those operating at 1.8 volts or greater, current source isolation circuits are traditionally inserted between the internal circuits and a noisy supply and ground to minimize the effects of clock jitter in sensitive circuits such as VCOs.
Conventionally, it has been assumed that isolating the power and ground circuits for each timing circuit on an IC was the way to reduce the jitter in the timing circuit. FIG. 1 illustrates an embodiment of such presently recommended practice for a conventional embedded PLL timing circuit, one with separate power and ground supplies. The circuit diagram 100 of FIG. 1 includes three representative sections of the chip 101, an Input/Output (“I/O”) circuit 102, a core circuit 104, and a timing circuit 106 such as a Phase Lock Loop (PLL) or a Delay Lock Loop (DLL) circuit. As shown in FIG. 1, each of the three representative circuits is provided with its own supply voltage as well as its own ground supply. Specifically, I/O circuit 102 is provided with a first +3.3 volt power supply 110, and a 3.3 volt ground connection 112, while core circuit 104 is provided with a +1.0 volt power supply 116, and a 1.0 volt ground connection 118. Similarly, the timing circuit 106 in such conventional arrangements is connected to both a +3.3 volt power supply 122 and a +1.0 volt power supply 124, as well as complementary ground supplies of 3.3 volts 126 and 1.0 volts 128; these supply potentials being separate/distinct to provide the isolation between the timing circuits previously sought.
A chip 101, as described in connection with FIG. 1, is typically fabricated on a grounded, P-doped substrate. The ground pins are generally connected to the P-doped substrate with transistor ground taps to prevent circuit problems such as latch up. With respect to such substrate and grounding issues, illustrations of ground nodes and associated resistive connections to such ground nodes of exemplary chip 101 are set forth next in connection with FIG. 2. Common recommended usage excludes the use of metal to combine ground nodes for all on-chip circuits.
FIG. 2 is a representative cross-sectional view of chip 101, illustrating the resistive connectivity of ground nodes to a P-doped substrate 202. As shown in FIG. 2, a first ground node 206 is shown connected to the 1.0 volt ground supply 118 to the core circuit, a second ground node 208 is shown connected to the 1.0 volt ground supply 128 to the timing circuit, a third ground node 210 is shown connected to the 3.3 volt ground supply 126 to the timing circuit, and a fourth ground node 212 is shown connected to the 3.3 volt ground supply 112 to the I/O circuit. Each of the respective ground nodes, 206, 208, 210 and 212, in turn, is shown as being connected to the P-doped substrate 202 by means of a representative resistance, 226, 228, 230 and 232, respectively. The model representative resistances, 226, 228, 230 and 232, are indicative of the differing phase delays of the discharge pathways, especially with respect to the sensitivity many current low voltage technologies have concerning such impedance.
Accordingly, there is a need for timing circuits that attenuate the effects of ground current surges from chip output drivers in order to obtain low-noise timing circuits.